A primary goal in many logic designs is to minimize, or at least control, the timing skew introduced by varying propagation delays through the logic circuits. Sometimes it is necessary to add skew while other times it is desirable to reduce skew to achieve balanced rise and fall times as per the application. A basic inverter circuit may comprise, for example, a P-channel transistor and an N-channel transistor serially coupled between first and second power supply conductors and responsive to a common input signal for providing an inverted output signal at the common drains thereof. It is well understood in the art that P-channel transistors are inherently weaker (provide less drive) given the same geometry as an N-channel device. A common practice is to make the P-channel transistor say 2.5 times the area of the N-channel transistor to provide approximately equal drive levels for the output signal. However, if the input signal is already skewed with unequal rise and fall times, equal drive levels of the P-channel and N-channel transistors will only serve to propagate the existing timing skew.
Conventional techniques teach adjusting the sizes of the P-channel and N-channel transistors to compensate for the anticipated timing skew of the input signal and achieve the desired rise and fall times of the output signal. For example, if the rising edge of the output signal is too slow relative to the falling edge of the same, the respective sizes of the P-channel and N-channel devices may be increased from a ratio of 250/100 microns to 300/100 microns. The larger P-channel transistor pulls the output node toward the positive power supply conductor more rapidly and decreases the rise time (increase positive slew rate) of the output signal. Furthermore, increasing the size of the P-channel transistor increases the threshold voltage of the inverter circuit causing it to switch at a higher level of the input signal. Another option is to leave the P-channel transistor alone and decrease the size of the N-channel transistor to a ratio of 250/70 microns. This option also increases the threshold level of the inverter circuit. Unfortunately, by decreasing the size of the N-channel transistor one has also reduced the pull-down drive of the inverter circuit.
The aforedescribed compensation technique of manipulating P-channel and N-channel transistor sizes has a number of drawbacks. One of the drawbacks of increasing the size of the P-channel transistor, or decreasing the size of the N-channel transistor, to achieve faster rise times for the output signal is the associated increase in the fall time (slower zero-going slew rate) of the output signal. Increasing the size of the P-channel transistor alone has the effect of increasing the threshold voltage and turning the N-channel device on at a higher level of the input signal which increases the fall time of the output signal. Alternately, using a smaller N-channel transistor provides less drive strength to discharge the output node and pull the output signal low which also increases the fall time of the output signal. Hence, manipulating the sizes of the P-channel and N-channel transistors may speed up one edge, but not without adversely effecting the opposite edge.
The output loading is also a concern when attempting to customize transistor sizes and compensate for timing skew. Since decreasing the size of the N-channel device inherently provides less drive to the output load and increases the fall time, there is effectively a limit to how small the N-channel transistor can be made and still drive the output load. On the other hand, increasing the size of the P-channel transistor increases its gate capacitance and the input loading as seen by the external circuitry driving the inverter. Thus, whatever approach one chooses for adjusting timing skew there is a penalty adversely affecting the slew rate of the opposite edge or the input and output loading.
Another concern with adjusting P-channel and N-channel transistors is the limitation in build-up ratios. For example, in a string of serially coupled inverters it may be necessary to increase the size of each subsequent transistor inverter stage over the previous transistor inverter stage through a build-up ratio to achieve some ultimate drive capability. Practical limitations on the output drive of any conventional single inverter stage allows transistor build-up ratios of only two or three times between adjacent inverter stages without overloading the previous stage and sacrificing operating speed. Yet, space limitations in the application may not permit a long string of inverter stages to achieve the ultimate drive capability. Therefore, one must compromise between higher build-up ratios and lower operating speed.
Hence, what is needed is an improved CMOS logic circuit having independently selectable rise and fall times without adversely affecting the opposite edge or the input and output loading thereof. Furthermore, it is desirable to achieve higher build-up ratios without sacrificing operating speed.